Wire Optimization and Delay Reduction for High-Performance on-ChipInterconnection in GALS Systems

Collection with item attached
2017
Item details URL
http://open-repository.kisti.re.kr/cube/handle/open_repository/487037.do
DOI
10.4218/etrij.17.0116.0052
Title
Wire Optimization and Delay Reduction for High-Performance on-ChipInterconnection in GALS Systems
Description
This work was supported by Institute for Information & communicationsTechnology Promotion (IITP) grant funded by the Korea government (MSIT)(NO. B0101-16-0548, Low-power and High-density Micro Server SystemDevelopment for Cloud Infrastructure).
abstract
To address the wire complexity problem in large-scale globally asynchronous, locally synchronous systems, a current-mode ternary encoding scheme was devised for a two-phase asynchronous protocol. However, for data transmission through a very long wire, few studies have been conducted on reducing the long propagation delay in current- mode circuits. Hence, this paper proposes a current steering logic (CSL) that is able to minimize the long delay for the devised current-mode ternary encoding scheme. The CSL creates pulse signals that charge or discharge the output signal in advance for a short period of time, and as a result, helps prevent a slack in the current signals. The encoder and decoder circuits employing the CSL are implemented using 0.25-mu m CMOS technology. The results of an HSPICE simulation show that the normal and optimal mode operations of the CSL achieve a delay reduction of 11.8% and 28.1%, respectively, when compared to the original scheme for a 10-mm wire. They also reduce the power-delay product by 9.6% and 22.5%, respectively, at a data rate of 100 Mb/s for the same wire length.
provenance
Made available in Cube on 2018-09-28T16:23:34Z (GMT). No. of bitstreams: 0
language
English
author
Oh, Myeong-Hoon
Kim, Young Woo
Kim, Hag Young
Kim, Young-Kyun
Kim, Jin-Sung
accessioned
2018-09-28T16:23:34Z
available
2018-09-28T16:23:34Z
issued
2017
citation
ETRI JOURNAL(39): 4
issn
1225-6463
uri
http://open-repository.kisti.re.kr/cube/handle/open_repository/487037.do
Funder
과학기술정보통신부
Funding Program
SW컴퓨팅산업원천기술개발
Project ID
1711055608
Jurisdiction
Rep.of Korea
Project Name
Low-power and High-density Micro Server System Development for Cloud Infrastructure
rights
openAccess
subject
High-performance interconnection
Current mode circuit
Asynchronousprotocol
Delay insensitive
CSL
type
article


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