A Hybrid Gate Dielectrics of Ion Gel with Ultra-Thin Passivation Layerfor High-Performance Transistors Based on Two-Dimensional SemiconductorChannels

Collection with item attached
2017
Item details URL
http://open-repository.kisti.re.kr/cube/handle/open_repository/473669.do
DOI
10.1038/s41598-017-14649-6
Title
A Hybrid Gate Dielectrics of Ion Gel with Ultra-Thin Passivation Layerfor High-Performance Transistors Based on Two-Dimensional SemiconductorChannels
Description
This work was supported by National Research Foundation of Korea (NRF)grant funded by the Korea government (MSIP) (No. 2016R1C1B2007336 andNo. 2017R1A2B4004560). This work was also supported by New TechnologyCommercialization Support Program for Young Researchers (2016) funded bythe Busan metropolitan city and Busan Institute of S&T Evaluation andPlanning (BISTEP).
abstract
We propose a hybrid gate structure for ion gel dielectrics using an ultra-thin Al2O3 passivation layer for realizing high-performance devices based on electric-double-layer capacitors. Electric-double-layer transistors can be applied to practical devices with flexibility and transparency as well as research on the fundamental physical properties of channel materials; however, they suffer from inherent unwanted leakage currents between electrodes, especially for channel materials with low off-currents. Therefore, the Al2O3 passivation layer was introduced between the metal electrodes and ion gel film as a leakage current barrier; this simple approach effectively reduced the leakage current without capacitance degradation. In addition, we confirmed that a monolayer MoS2 transistor fabricated with the proposed hybrid gate dielectric exhibited remarkably enhanced device properties compared to a transistor using a normal ion gel gate dielectric. Our findings on a simple method to improve the leakage current properties of ion gels could be applied extensively to realize high-performance electric-double-layer transistors utilizing various channel materials.
provenance
Made available in Cube on 2018-09-28T10:25:45Z (GMT). No. of bitstreams: 0
language
English
author
Jo, Hyunjin
Choi, Jeong-Hun
Hyun, Cheol-Min
Seo, Seung-Young
Kim, Da Young
Kim, Chang-Min
Lee, Myoung-Jae
Kwon, Jung-Dae
Moon, Hyoung-Seok
Kwon, Se-Hun
Ahn, Ji-Hoon
orcid
Ahn, Ji-hoon/0000-0001-6928-4038; Lee, Myoung-Jae/0000-0003-2626-0460
accessioned
2018-09-28T10:25:45Z
available
2018-09-28T10:25:45Z
issued
2017
citation
SCIENTIFIC REPORTS(7)
issn
2045-2322
uri
http://open-repository.kisti.re.kr/cube/handle/open_repository/473669.do
Funder
과학기술정보통신부
Funding Program
개인기초연구(미래부)
Project ID
1711053079
Jurisdiction
Rep.of Korea
Project Name
Low temperature deposition of two-dimensional semiconductor materials for wafer-scale flexible device integration
rights
openAccess
type
article


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